1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to a test structure for testing integrated circuits.
2. Description of the Related Art
The use of conductive balls, such as solder balls, to make electrical connection to a bond pad is a known method to make electrical connection to electrical circuitry of a semiconductor die. Conductive ball packaging is one type of semiconductor packaging known in the industry as flip chip interconnection. As geometries in semiconductors continue to shrink in size due to improvements in the technology for making semiconductors, the sizes of bond pad regions have become smaller, resulting in increased stress to the bond pad structure when physical connection is made to the semiconductor die. Additional mechanical integrity problems are created by the interconnect structures used with the manufacturing smaller geometry semiconductors. For example, bond pad structures fabricated with copper interconnect metallization and low dielectric constant (low-k) dielectrics are susceptible to mechanical damage during the bonding process, due to the lower Young's modulus and lower fracture toughness of such materials. As a result, the underlying stack of metal and dielectric layers in such bond pad structures may mechanically fracture more easily or otherwise be subject to mismatch stresses (such as generated during die attach process).
To detect such device defects, a variety of techniques have been proposed for characterizing the properties and the integration capability of these films, such as nano-indentation and four-point bend delamination tests for mechanical and adhesion properties, and die pull tests and thermal cycling tests for characterizing the behavior of low-k films in a flip chip package. However, these tests have one or more drawbacks in failing to quickly and reliably provide feedback on the quality of the mechanical integration of the back end of the line (BEOL) structures.
Accordingly, there is a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.